65C816: PC, machine code, mnemonic, operands, registers (A, X, Y, SP, P), flags (NVTBDIZCR) Cycles SL F Cycle
008000: 78 SEI A:0000 X:0000 Y:0000 SP:01FE P:34 nvMXdIzcR Cy: 35 LY: 0 F-Cy: 0
008001: 9C 00 42 STZ $4200 A:0000 X:0000 Y:0000 SP:01FE P:34 nvMXdIzcR Cy: 50 LY: 0 F-Cy: 0
008004: 9C 0C 42 STZ $420C A:0000 X:0000 Y:0000 SP:01FE P:34 nvMXdIzcR Cy: 74 LY: 0 F-Cy: 0
008007: 9C 0B 42 STZ $420B A:0000 X:0000 Y:0000 SP:01FE P:34 nvMXdIzcR Cy: 98 LY: 0 F-Cy: 0
00800A: 9C 40 21 STZ $2140 A:0000 X:0000 Y:0000 SP:01FE P:34 nvMXdIzcR Cy: 122 LY: 0 F-Cy: 0
00800D: 9C 41 21 STZ $2141 A:0000 X:0000 Y:0000 SP:01FE P:34 nvMXdIzcR Cy: 146 LY: 0 F-Cy: 0
008010: 9C 42 21 STZ $2142 A:0000 X:0000 Y:0000 SP:01FE P:34 nvMXdIzcR Cy: 170 LY: 0 F-Cy: 0
008013: 9C 43 21 STZ $2143 A:0000 X:0000 Y:0000 SP:01FE P:34 nvMXdIzcR Cy: 194 LY: 0 F-Cy: 0
008016: A9 80 LDA #$80 A:0000 X:0000 Y:0000 SP:01FE P:34 nvMXdIzcR Cy: 218 LY: 0 F-Cy: 0
008018: 8D 00 21 STA $2100 A:0080 X:0000 Y:0000 SP:01FE P:B4 NvMXdIzcR Cy: 230 LY: 0 F-Cy: 0
00801B: 18 CLC A:0080 X:0000 Y:0000 SP:01FE P:B4 NvMXdIzcR Cy: 254 LY: 0 F-Cy: 0
00801C: FB XCE A:0080 X:0000 Y:0000 SP:01FE P:B4 NvMXdIzcR Cy: 266 LY: 0 F-Cy: 0
00801D: C2 38 REP #$38 A:0080 X:0000 Y:0000 SP:01FE P:B5 NvMXdIzCR Cy: 278 LY: 0 F-Cy: 0
00801F: A9 00 LDA #$00 A:0080 X:0000 Y:0000 SP:01FE P:8D NvmxdIzCR Cy: 296 LY: 0 F-Cy: 0
008022: 5B TCD A:0000 X:0000 Y:0000 SP:01FE P:0F nvmxdIZCR Cy: 314 LY: 0 F-Cy: 0
008023: A9 FF LDA #$FF A:0000 X:0000 Y:0000 SP:01FE P:0F nvmxdIZCR Cy: 326 LY: 0 F-Cy: 0
008026: 1B TCS A:01FF X:0000 Y:0000 SP:01FE P:0D nvmxdIzCR Cy: 344 LY: 0 F-Cy: 0
I'm working on a SNES core as part of my adaptive sync project. I've reached the point where I can start running code and trace logging, above are the first few instructions of SMW. There are many many bugs in the CPU to work out still but I'm pretty happy with how it turned out architecturally. Of course the CPU is the easy part of SNES emulation. I'm hoping to have this core up and running in ~1 year.