A few updates / thoughts:
NES: Power up timing and state is pretty much resolved now. It turns out NESDev folks had already worked out DMC state last year, so that was cool. I just need to do a couple hardware tests now to sort out the last couple details. I also tried matching up to Mesen, and it looks like Mesen state should be -1 cycle from NESHawk. When I use that state in NESHawk I do get runs that sync on console (with lower probability, about 50% less likely then the state I have now, but could be console dependent) but those same movies then do not sync in Mesen. Some memory access timings had speculatively been changed in 0.9.9, so they probably just need to be changed back. Anyway, there aren't many obstacles left for NES , probably by the end of the year most runs will be working on console.
SNES: BSNES v115 was unexpectedly added to BizHawk recently, hopefully someone can try the 2 versions of the SOS submission,
#7152: Samsara's SNES SOS in 04:34.08 . They may still both desync, but if v115 works where v78 doesn't, that might be a big deal for seeing more working SNES runs.
GBA: I had run across this GBA emulator recently that seems to do things at a finer level of timing detail then mGBA:
https://github.com/fleroviux/NanoBoyAdvance . A lot of necessary timing tests haven't even been written yet, so it probably doesn't matter much right now, but maybe worth keeping an eye on.
I'm not sure what to focus on next once the remaining NES issues are sorted out. I'm open to suggestions, there's so much to do it's hard to decide where to start.
As it turns out, the way to actually get this correct is an undocumented behavior!
When a DMC DMA happens, the address bus changes so that the DMC unit can read a sample value. The controller glitch occurs when the DMA happens on a controller read cycle. The controller shift register sees the address bus change to the DMA address and then back again, resulting in double clocking of the controller.
However, if the DMA address happens to have the same bits set as the controller register (I think it is (DMA ADDR & 0x401F) == 0x4016 but am still narrowing it down) then there will not be an extra clock.
I guess in hind sight this kind of makes sense, but still it's pretty neat to discover a new behavior on a system as well studied as the NES.
Getting really close to correct DMC emulation now.